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MRF89XA
2.14
2.14.1
General Configuration Registers
GENERAL CONFIGURATION
REGISTER DETAILS
REGISTER 2-1:
GCONREG: GENERAL CONFIGURATION REGISTER
(ADDRESS:0X00) (POR:0X28)
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
bit 7
CMOD<2:0>
FBS<1:0>
VCOT<1:0>
RPS
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-5
bit 4-3
bit 2-1
bit 0
CMOD<2:0>: Chip Mode bits
These bits select the mode of operation of the transceiver.
111 = Reserved; do not use
110 = Reserved; do not use
101 = Reserved; do not use
100 = Transmit mode
011 = Receive mode
010 = Frequency Synthesizer mode
001 = Stand-by mode (default)
000 = Sleep mode
FBS<1:0>: Frequency Band Select bits
These bits set the frequency band to be used in Sub-GHz range.
11 = Reserved
10 = 950-960 MHz or 863- 870 MHz (application circuit dependant)
01 = 915-928 MHz (default)
00 = 902-915 MHz
VCOT<1:0>: TX bits
For each AFC cycle run, these bits will toggle between logic ‘ 1 ’ and logic ‘ 0 ’.
11 = Vtune + 180 mV typ
10 = Vtune + 120 mV typ
01 = Vtune + 60 mV typ
00 = Vtune determined by tank inductors values (default)
RPS: RPS Select bit
This bit selects between the two sets of frequency dividers of the PLL, Ri/Pi/Si. For more information,
see Section 3.2.7, Frequency Calculation .
1 = Enable R2/P2/S2 set
0 = Enable R1/P1/S1 set (default)
DS70622C-page 30
Preliminary
? 2010–2011 Microchip Technology Inc.
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